SOLUTIONS 167
Sarah L. Harris and David Money Harris, Digital Design and Computer Architecture: ARM® Edition © 2015 by Elsevier
Inc. Exercise Solutions
5.45 (e)
SystemVerilog
module prefixaddpipe(input logic clk, cin,
input logic [31:0] a, b,
output logic [31:0] s, output cout);
// p and g prefixes for rows 0 - 5
logic [30:0] p0, p1, p2, p3, p4, p5;
logic [30:0] g0, g1, g2, g3, g4, g5;
logic p_1_0, p_1_1, p_1_2, p_1_3, p_1_4, p_1_5,
g_1_0, g_1_1, g_1_2, g_1_3, g_1_4, g_1_5;
// pipeline values for a and b
logic [31:0] a0, a1, a2, a3, a4, a5,
b0, b1, b2, b3, b4, b5;
// row 0
flop #(2) flop0_pg_1(clk, {1'b0,cin}, {p_1_0,g_1_0});
pandg row0(clk, a[30:0], b[30:0], p0, g0);
// row 1
flop #(2) flop1_pg_1(clk, {p_1_0,g_1_0}, {p_1_1,g_1_1});
flop #(30) flop1_pg(clk,
{p0[29],p0[27],p0[25],p0[23],p0[21],p0[19],p0[17],p0[15],
p0[13],p0[11],p0[9],p0[7],p0[5],p0[3],p0[1],
g0[29],g0[27],g0[25],g0[23],g0[21],g0[19],g0[17],g0[15],
g0[13],g0[11],g0[9],g0[7],g0[5],g0[3],g0[1]},
{p1[29],p1[27],p1[25],p1[23],p1[21],p1[19],p1[17],p1[15],
p1[13],p1[11],p1[9],p1[7],p1[5],p1[3],p1[1],
g1[29],g1[27],g1[25],g1[23],g1[21],g1[19],g1[17],g1[15],
g1[13],g1[11],g1[9],g1[7],g1[5],g1[3],g1[1]});
blackbox row1(clk,
{p0[30],p0[28],p0[26],p0[24],p0[22],
p0[20],p0[18],p0[16],p0[14],p0[12],
p0[10],p0[8],p0[6],p0[4],p0[2],p0[0]},
{p0[29],p0[27],p0[25],p0[23],p0[21],
p0[19],p0[17],p0[15],p0[13],p0[11],
p0[9],p0[7],p0[5],p0[3],p0[1],1'b0},
{g0[30],g0[28],g0[26],g0[24],g0[22],
g0[20],g0[18],g0[16],g0[14],g0[12],
g0[10],g0[8],g0[6],g0[4],g0[2],g0[0]},
{g0[29],g0[27],g0[25],g0[23],g0[21],
g0[19],g0[17],g0[15],g0[13],g0[11],
g0[9],g0[7],g0[5],g0[3],g0[1],g_1_0},
{p1[30],p1[28],p1[26],p1[24],p1[22],p1[20],
p1[18],p1[16],p1[14],p1[12],p1[10],p1[8],
p1[6],p1[4],p1[2],p1[0]},
{g1[30],g1[28],g1[26],g1[24],g1[22],g1[20],
g1[18],g1[16],g1[14],g1[12],g1[10],g1[8],
g1[6],g1[4],g1[2],g1[0]});
// row 2
flop #(2) flop2_pg_1(clk, {p_1_1,g_1_1}, {p_1_2,g_1_2});
flop #(30) flop2_pg(clk,
{p1[28:27],p1[24:23],p1[20:19],p1[16:15],p1[12:11],